数字系统设计 - 触发器 Flip-Flops原理

触发器Flip-Flops

2ZDMC–Lec.#8RSQQRSQRSQQQSRMemorywithCross-coupledGatesCross-coupledNORgatesSimilartoinverterpair,withcapabilitytoforceoutputto0(reset=1)or1(set=1)

Cross-coupledNANDgatesSimilartoinverterpair,withcapabilitytoforceoutputto0(reset=0)or1(set=0)

复习

NANDLatch3ZDMC–Lec.#8复习

SettingtheLatch(FF)PulsingtheSETinputtothe0statewhen(a)Q=0priortoSETpulse;(b)Q=1priortoSETpulse.Notethat,inbothcases,QendsupHIGH.4ZDMC–Lec.#8复习

ResettingtheLatch(FF)PulsingtheRESETinputtotheLOWstatewhen(a)Q=0priortoRESETpulse;(b)Q=1priortoRESETpulse.Ineachcase,QendsupLOW.5ZDMC–Lec.#8复习

SummaryofNADNLatch(a)NANDlatch;(b)functiontable.6ZDMC–Lec.#8

AlternateRepresentations(a)NANDlatchequivalentrepresentation;(b)simplifiedblocksymbol.7ZDMC–Lec.#8

NORGateLatch(a)NORgatelatch(b)functiontable(c)simplifiedblocksymbol8ZDMC–Lec.#8

Analyzeanddescribetheoperationofthecircuit9ZDMC–Lec.#8

10ZDMC–Lec.#8ObservedR-SLatchBehaviorVerydifficulttoobserveR-Slatchinthe1-1stateOneofRorSusuallychangesfirstAmbiguouslyreturnstostate0-1or1-0Aso-calledraceconditionOrnon-deterministictransitionSR=00SR=00QQ

01QQ

10QQ

00SR=10SR=01SR=00SR=10SR=00SR=01SR=11SR=11SR=01SR=10SR=11复习

11ZDMC–Lec.#8clockRandSchangingstablechangingstablestableClocks(cont’d)ControllinganR-SlatchwithaclockCantletRandSchangewhileclockisactive(allowingRandStopass)OnlyhavehalfofclockperiodforsignalchangestopropagateSignalsmustbestablefortheotherhalfofclockperiodclockSQQRRS复习

12ZDMC–Lec.#8Master-SlaveStructureBreakflowbyalternatingclocks(likeanair-lock)UsepositiveclocktolatchinputsintooneR-SlatchUsenegativeclocktochangeoutputswithanotherR-SlatchViewpairasonebasicunitmaster-slaveflip-floptwiceasmuchlogicoutputchangesafewgatedelaysafterthefallingedge

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